1. Field of the Invention
The present invention relates to a DLL (Delay Locked Loop) circuit and a semiconductor device having the DLL circuit incorporated therein, and more particularly relates to a DLL circuit with a reduced time required for locking and a semiconductor device having the DLL circuit incorporated therein.
2. Description of Related Art
In recent years, a synchronous memory that operates in synchronization with a clock signal has been widely used as a main memory for personal computers. To set inputted/outputted data precisely in synchronization with an external clock signal especially in a DDR (Double Data Rate) synchronous memory, a DLL circuit that generates an internal clock signal in synchronization with an external clock signal is used (see Japanese Patent Application Laid-open No. 2008-217947).
The DLL circuit detects whether a replica clock signal is advanced or delayed with respect to an external clock signal and adjusts the amount of delay of a variable delay circuit based on a result of detection, so that their phases match each other.
However, because the amount of delay is adjusted by one pitch at a time in conventional DLL circuits, when the amount of phase difference between an external clock signal and a replica clock signal, that is, the time difference between an active edge of the external clock signal and an active edge of the replica clock signal is large, the number of adjusting operations is increased, and thus there is a problem that a time required for locking the DLL circuit is extended.